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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MCM6946/D
512K x 8 Bit Static Random Access Memory
The MCM6946/SCM6946 is a 4,194,304-bit static random access memory organized as 524,288 words of 8 bits. Static design eliminates the need for external clocks or timing strobes. The MCM6946/SCM6946 is equipped with chip enable (E) and output enable (G) pins, allowing for greater system flexibility and eliminating bus contention problems. Either input, when high, will force the outputs into high impedance. The MCM6946 is available in a 400 mil, 36-lead surface-mount SOJ package. * * * * * * * Single 3.3 V - 5%, + 10% Power Supply Fast Access Time: 8/10/12/15 ns Equal Address and Chip Enable Access Time All Inputs and Outputs are TTL Compatible Three-State Outputs Power Operation: 195/185 / 180 / 175 mA Maximum, Active AC Available in TSOP or SOJ Packages
MCM6946 SCM6946
YJ PACKAGE 400 MIL SOJ CASE 893-02
TS PACKAGE 44-LEAD TSOP TYPE II CASE 924A-02
PIN NAMES BLOCK DIAGRAM
A A A A A A A A A A ROW DECODER A0 - A18 . . . . . . . . . . . . . . . Address Inputs W . . . . . . . . . . . . . . . . . . . . . . . Write Enable G . . . . . . . . . . . . . . . . . . . . . Output Enable E . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable DQ . . . . . . . . . . . . . . . . . Data Input/Output NC . . . . . . . . . . . . . . . . . . . . No Connection VDD . . . . . . . . . . . . . + 3.3 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . . . Ground
MEMORY MATRIX
DQ INPUT DATA CONTROL DQ A A A
COLUMN I/O COLUMN DECODER
A
A
A
A
A
A DQ
E
W G
DQ
REV 8 1/29/99
(c) Motorola, Inc. 1999 MOTOROLA FAST SRAM
MCM6946*SCM6946 1
PIN ASSIGNMENTS 400 MIL SOJ
A A A A A E DQ DQ VDD VSS DQ DQ W A A A A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC A A A A G DQ DQ VSS VDD DQ DQ A A A A A NC NC NC A A A A A E DQ DQ VDD VSS DQ DQ W A A A A A NC NC
TSOP TYPE II
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 NC NC NC A A A A G DQ DQ VSS VDD DQ DQ A A A A A NC NC NC
TRUTH TABLE (X = Don't Care)
E H L L L G X H L X W X H H L Mode Not Selected Output Disabled Read Write I/O Pin High-Z High-Z Dout High-Z Cycle -- -- Read Write Current ISB1, ISB2 IDDA IDDA IDDA
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating Power Supply Voltage Relative to VSS Voltage Relative to VSS for Any Pin Except VDD Output Current (per I/O) Power Dissipation Temperature Under Bias Operating Temperature Storage Temperature -- Plastic Symbol VDD Vin, Vout Iout PD Tbias TA Tstg Value - 0.5 to 5.0 - 0.5 to VDD + 0.5 20 1.0 - 10 to 85 0 to 70 - 55 to 150 Unit V V mA W C C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high-impedance circuits. This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
SCM6946*MCM6946 2
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V - 5%, + 10%, TA = 0 to 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage Symbol VDD VIH VIL Min 3.135 2.2 - 0.5* Typ 3.3 -- -- Max 3.6 VDD + 0.3** 0.8 Unit V V V
* VIL (min) = - 0.5 V dc; VIL (min) = - 2.0 V ac (pulse width 2.0 ns). ** VIH (max) = VDD + 0.3 V dc; VIH (max) = VDD + 2.0 V ac (pulse width 2.0 ns).
DC CHARACTERISTICS
Parameter Input Leakage Current (All Inputs, Vin = 0 to VDD) Output Leakage Current (E = VIH, Vout = 0 to VDD) Output Low Voltage (IOL = + 8.0 mA) Output High Voltage (IOH = - 4.0 mA) Symbol Ilkg(I) Ilkg(O) VOL VOH Min -- -- -- 2.4 Max 1.0 1.0 0.4 -- Unit A A V V
POWER SUPPLY CURRENTS
Parameter AC Active Supply Current (Iout = 0 mA, VDD = Max) SCM6946-8: tAVAV = 8 ns MCM6946-10: tAVAV = 10 ns MCM6946-12: tAVAV = 12 ns MCM6946-15: tAVAV = 15 ns SCM6946-8: tAVAV = 8 ns MCM6946-10: tAVAV = 10 ns MCM6946-12: tAVAV = 12 ns MCM6946-15: tAVAV = 15 ns Symbol IDD 0 to 70C 195 185 180 175 55 50 50 45 20 Unit mA
AC Standby Current (VDD = Max, E = VIH, No Other Restrictions on Other Inputs)
ISB1
mA
CMOS Standby Current (E VDD - 0.2 V, Vin VSS + 0.2 V or VDD - 0.2 V) (VDD = Max, f = 0 MHz)
ISB2
mA
CAPACITANCE (f = 1.0 MHz, dV = 3.3 V, TA = 25C, Periodically Sampled Rather Than 100% Tested)
Parameter Input Capacitance Input/Output Capacitance All Inputs Except Clocks and DQs E, G, W DQ Symbol Cin Cck CI/O Typ 4 5 5 Max 6 8 8 Unit pF pF
MOTOROLA FAST SRAM
MCM6946*SCM6946 3
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V - 5%, + 10%, TA = 0 to 70C, Unless Otherwise Noted)
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
READ CYCLE TIMING (See Notes 1 and 2)
SCM6946-8 Parameter P Read Cycle Time Address Access Time Enable Access Time Output Enable Access Time Output Hold from Address Change Enable Low to Output Active Output Enable Low to Output Active Enable High to Output High-Z Output Enable High to Output High-Z Symbol S bl tAVAV tAVQV tELQV tGLQV tAXQX tELQX tGLQX tEHQZ tGHQZ Min 8 -- -- -- 2 3 0 0 0 Max -- 8 8 4 -- -- -- 4 4 MCM6946-10 Min 10 -- -- -- 2 3 0 0 0 Max -- 10 10 5 -- -- -- 5 5 MCM6946-12 Min 12 -- -- -- 2 3 0 0 0 Max -- 12 12 6 -- -- -- 6 6 MCM6946-15 Min 15 -- -- -- 2 3 0 0 0 Max -- 15 15 7 -- -- -- 7 7 Unit Ui ns ns ns ns ns ns ns ns ns 5, 6, 7 5, 6, 7 5, 6, 7 5, 6, 7 4 Notes N 3
NOTES: 1. W is high for read cycle. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. All read cycle timings are referenced from the last valid address to the first transitioning address. 4. Addresses valid prior to or coincident with E going low. 5. At any given voltage and temperature, tEHQZ max tELQX min, and tGHQZ max tGLQX min, both for a given device and from device to device. 6. Transition is measured 200 mV from steady-state voltage. 7. This parameter is sampled and not 100% tested. 8. Device is continuously selected (E VIL, G VIL).
t
t
TIMING LIMITS
The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time. On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.
OUTPUT Z0 = 50
RL = 50
VL = 1.5 V
Figure 1. AC Test Load
SCM6946*MCM6946 4
MOTOROLA FAST SRAM
READ CYCLE 1 (See Note 8)
tAVAV A (ADDRESS) tAXQX Q (DATA OUT) PREVIOUS DATA VALID tAVQV DATA VALID
READ CYCLE 2 (See Note 4)
tAVAV A (ADDRESS) tELQV E (CHIP ENABLE) tELQX G (OUTPUT ENABLE) tGLQV tGLQX Q (DATA OUT) HIGH-Z tAVQV SUPPLY CURRENT IDD ISB DATA VALID tGHQZ tEHQZ
MOTOROLA FAST SRAM
MCM6946*SCM6946 5
WRITE CYCLE 1 (W Controlled; See Notes 1, 2, and 3)
SCM6946-8 Parameter P Write Cycle Time Address Setup Time Address Valid to End of Write Address Valid to End of Write (G High) Write Pulse Width Write Pulse Width (G High) Data Valid to End of Write Data Hold Time Write Low to Data High-Z Write High to Output Active Write Recovery Time Symbol S bl tAVAV tAVWL tAVWH tAVWH tWLWH tWLEH tWLWH tWLEH tDVWH tWHDX tWLQZ tWHQX tWHAX Min 8 0.5 8 7 8 7 6 0 0 3 0 Max -- -- -- -- -- -- -- -- 4 -- -- MCM6946-10 Min 10 0.5 9 8 9 8 6 0 0 3 0 Max -- -- -- -- -- -- -- -- 5 -- -- MCM6946-12 Min 12 0.5 10 9 10 9 6 0 0 3 0 Max -- -- -- -- -- -- -- -- 6 -- -- MCM6946-15 Min 15 0.5 12 10 12 10 7 0 0 3 0 Max -- -- -- -- -- -- -- -- 7 -- -- Unit Ui ns ns ns ns ns ns ns ns ns ns ns 5, 6, 7 5, 6, 7 Notes N 4
NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. If G goes low coincident with or after W goes low, the output will remain in a high-impedance state. 4. All write cycle timings are referenced from the last valid address to the first transitioning address. 5. Transition is measured 200 mV from steady-state voltage. 6. This parameter is sampled and not 100% tested. 7. At any given voltage and temperature, tWLQZ max < tWHQX min, both for a given device and from device to device.
WRITE CYCLE 1 (W Controlled; See Notes 1, 2, and 3)
tAVAV A (ADDRESS) tAVWH E (CHIP ENABLE) tWLWH tWLEH W (WRITE ENABLE) tAVWL D (DATA IN) tWLQZ Q (DATA OUT) HIGH-Z HIGH-Z tDVWH DATA VALID tWHQX tWHDX tWHAX
SCM6946*MCM6946 6
MOTOROLA FAST SRAM
WRITE CYCLE 2 (E Controlled; See Notes 1, 2, and 3)
SCM6946-8 Parameter P Write Cycle Time Address Setup Time Address Valid to End of Write Address Valid to End of Write (G High) Enable Pulse Width Enable Pulse Width (G High) Data Valid to End of Write Data Hold Time Write Recovery Time Symbol S bl tAVAV tAVEL tAVEH tAVEH tELEH, tELWH tELEH, tELWH tDVEH tEHDX tEHAX Min 8 0 8 7 8 7 6 0 0 Max -- -- -- -- -- -- -- -- -- MCM6946-10 Min 10 0 9 8 9 8 6 0 0 Max -- -- -- -- -- -- -- -- -- MCM6946-12 Min 12 0 10 9 10 9 6 0 0 Max -- -- -- -- -- -- -- -- -- MCM6946-15 Min 15 0 12 10 12 10 7 0 0 Max -- -- -- -- -- -- -- -- -- Unit Ui ns ns ns ns ns ns ns ns ns 5, 6 5, 6 Notes N 4
NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. If G goes low coincident with or after W goes low, the output will remain in a high-impedance state. 4. All write cycle timing is referenced from the last valid address to the first transitioning address. 5. If E goes low coincident with or after W goes low, the output will remain in a high-impedance condition. 6. If E goes high coincident with or before W goes high, the output will remain in a high-impedance condition.
WRITE CYCLE 2 (E Controlled; See Notes 1, 2, and 3)
tAVAV A (ADDRESS) tAVEH tELEH E (CHIP ENABLE) tAVEL W (WRITE ENABLE) tDVEH D (DATA IN) DATA VALID tEHDX Q (DATA OUT) HIGH-Z tELWH tEHAX
ORDERING INFORMATION
(Order by Full Part Number) XCM
Motorola Memory Prefix Part Number
6946 XX XX XX
Shipping Method (R = Tape and Reel, Blank = Rails) Speed (8 = 8 ns, 10 = 10 ns, 12 = 12 ns, 15 = 15 ns) Package (YJ = 400 mil SOJ, TS = 44-Lead TSOP Type II)
Full Commercial Part Numbers -- SCM6946YJ8 SCM6946TS8
MCM6946YJ10 MCM6946YJ10R MCM6946TS10 MCM6946TS10R
MCM6946YJ12 MCM6946YJ12R MCM6946TS12 MCM6946TS12R
MCM6946YJ15 MCM6946YJ15R MCM6946TS15 MCM6946TS15R
MOTOROLA FAST SRAM
MCM6946*SCM6946 7
PACKAGE DIMENSIONS
YJ PACKAGE 400 MIL SOJ CASE 893-02 0.015 (0.381) T Y
2 ZONES 18 PLACES NOTE 3 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. TO BE DETERMINED AT PLANE -T-. 4. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.006 (0.15) PER SIDE. 5. DIMENSION A AND B INCLUDE MOLD MISMATCH AND ARE DETERMINED AT THE PARTING LINE.
0.007 (0.17)
36
M
TY
19
S
X
S
C E
-Y- P B R/2
1 18 36X R
R
R1
36X
F
A
-X- K 0.004 (0.1) T -T-
SEATING PLANE
36X
N
DIM A B C D E F G K L N P R R1
INCHES MIN MAX 0.920 0.930 0.395 0.405 0.128 0.148 0.015 0.020 0.082 --- 0.026 0.032 0.050 BSC 0.035 0.55 0.025 BSC 0.035 0.045 0.435 0.445 0.370 BSC 0.030 0.040
MILLIMETERS MIN MAX 23.37 23.62 10.03 10.29 3.25 3.76 0.38 0.51 2.08 --- 0.66 0.81 1.27 BSC 0.90 1.40 0.64 BSC 0.90 1.14 11.05 11.30 9.40 BSC 0.76 1.02
VIEW A
2X 34X
L G
36X D 0.007 (0.17)
M
TY
S
X
S
NOTE 3
VIEW A
SCM6946*MCM6946 8
MOTOROLA FAST SRAM
TS PACKAGE 44-LEAD TSOP TYPE II CASE 924A-02 B
44 23
VIEW A
E1 AA
1
22
A2 A A
22X
D
0.2
44X
M
E CB
0.004 (0.1) C
SEATING PLANE 4X
e /2
42X
e
C
NOTES: 1. DIMENSIONINS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETER. 3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTRUSION IS 0.15 PER SIDE. 4. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSIONS. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.58. DIM A A1 A2 b c D e E E1 L MILLIMETERS MIN MAX --- 1.20 0.05 0.15 0.95 1.05 0.30 0.45 0.12 0.21 18.28 18.54 0.80 BSC 11.56 11.96 10.03 10.29 0.40 0.60 0_ 5_
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado, 80217. 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPD, Strategic Planning Office, 141, 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan. 81-3-5487-8488
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MOTOROLA FAST SRAM
EEEE EEEE
b 0.2
M
c A1 L VIEW A ROTATED 90 _ CLOCKWISE
CB
SECTION A-A
40 PLACES
q
q
MCM6946/D MCM6946*SCM6946 9

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